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- Path: ns1.win.net!ecsd!ecs
- Newsgroups: comp.sys.m68k
- Message-ID: <273@ecsd.win.net>
- References: <4g9cfa$7h3@news.onramp.net>
- Reply-To: ecs@ecsd.win.net (Edward C. Schram)
- From: ecs@ecsd.win.net (Edward C. Schram)
- Date: Wed, 21 Feb 1996 04:44:58 GMT
- Subject: Re: CPU32 assembler question
-
-
- In article <4g9cfa$7h3@news.onramp.net>, Shay Collins (scollins@onramp.net) writes:
- >Hello,
- >I am working on a disassembler for the CPU32 instruction set.
- >
- >I have run into a feature of the as32 freeware assembler that
- >I don't understand, maybe you can explain it to me:
- >
- >when I do the following:
- >
- > ori.b #$55,($1234,a0)
- >
- >the assembler generates:
- >
- >0000310a 0028 0055 1234 ori.b #$55,($1234,a0)
- >
- >The instructions it generated seem to make sense, and follow
- >what I would expect - a mode 5 ori.b with a d16 displacement
- >of $1234.
- >
- >Now, when I do the following:
- >
- > ori.b #$55,($9000,a0)
- >
- >the assembler generates:
- >
- >00003116 0030 0055 0170 ori.b #$55,($9000,a0)
- > 0000 9000
- >
-
- The MSB is set here. Sign extension must be used therefore a 32
- bit displacement. Anything that has the MSB set is 32 bits.
-
-
-